The present disclosure relates to microprocessor design, and more specifically, to a dynamic microprocessor gate design tool for area/timing margin control.
Gate timing optimization in the physical synthesis of microprocessor designs may include improving or optimizing the timing of signals passing from an input through one or more gates to an output. Gate timing optimizations increase or decrease the area needed on a chip to implement the timing improvements because signal timing is affected by gate size. Power needed to operate the chip is also affected by increases or decreases in gate size during the optimization process.
The gate timing optimization process can include making small design transformations to gates, evaluating the changes to the circuit performance resulting from the gate change, and either accepting or rejecting the particular change. An important measurement for gate optimization is gate timing, which measures the units of time needed for a signal to travel from the signal input through one or more gates to the output. When a circuit is specified, there is often a timing requirement specified that indicates the expected time for the signal to travel from the input to another.
When the actual travel time exceeds the specified (expected) quantity of time, then the design process includes “closing” the gate timing to make the circuit meet the specified timing requirement. For example, the path of an input to output may leave the input at 0 time units and is expected to reach the output at 100 units. After testing, it may be determined that the signal is reaching the output at 120 units. Accordingly, this particular design has a “slack” of −20 units. Thus, engineers are tasked with increasing efficiency to speed the path by 20 time units to close the timing. The slack can be minimized by making various changes to the circuit, such as shortening wires, increasing gate sizes, etc., in order to reduce the −20 unit slack.
A gate design change may result in a change to a gate size that increases signal transmission speed from input to output. For example, a gate may be small in size, which may require a small amount of power to operate, but it cannot pass the signal quick enough to meet the specified transmission time. Although the time may be decreased by increasing the gate size, the design change comes at a cost to the design in terms of chip area needed to implement the design and power requirements for operating the chip. An optimization can include transforming a gate size to speed signal transmission by a few units of time. For example, a gate may be relatively small in size, but it cannot pass the signal quick enough to achieve a desired transmission time. Even if an improvement in speed is realized by increasing gate size, the improvements must be contrasted with cost in terms of chip size and manufacturing cost. It may be advantageous to provide a system and method that dynamically optimizes gate/time margins by maximizing time improvements while minimizing area, power and manufacturing costs.